This invention relates to a semiconductor device provided with a means for preventing the breakdown of an insulation layer.
In an MOS (Metal Oxide Semiconductor) device, for example, in which a gate electrode is provided, through an insulation layer, onto a silicon substrate portion between a source region and drain region and in which the potential of a silicon substrate portion beneath the insulation layer is controlled through said gate electrode, the input impedance is extremely high and the thickness of the insulation layer (for example, oxide layer) is very thin such as 400 to 1000 .ANG. and the insulation withstand voltage thereof is as low as 20 to 100 V. For this reason, when static electricity of a relatively high potential, for example, due to friction or the like, is applied to an input terminal of the gate electrode of the MOS device, the oxide layer (gate oxide layer) is easily broken down. Accordingly, a protective circuit, including a semiconductor element for clamping a high voltage from the input terminal to a specified value by the forward characteristic of the pn junction or the breakdown characteristic of the pn junction, so as to prevent the breakdown of the gate oxide layer of the MOS device to be protected, is necessarily connected to the input terminal of the gate electrode of the MOS device.
An example of this protective circuit is explained below with reference to FIG. 1. In FIG. 1, numeral 1 denotes an MOS transistor which is to be protected and numeral 2 denotes a signal input terminal to a gate electrode of that MOS transistor 1. Between the gate electrode of the MOS transistor 1 and the signal input terminal 2, there is connected a protective circuit 3. The protective circuit 3 includes a resistor R connected between the signal input terminal 2 and the gate electrode of the MOS transistor to be protected, and an MOS transistor 4 whose source-drain path is connected between the output end of this resistor R and a voltage source Vss (which is usually set at a level of 0 V) and in which the gate electrode and source are connected. Since the gate electrode of the MOS transistor 4 is connected to the voltage source Vss, it is possible to increase the protection of the gate oxide layer of the MOS transistor 1 (for example, an input MOS transistor of the MOS integrated circuit) by utilizing the fact that the breakdown voltage of the pn junction of the MOS transistor 4 on the drain side decreases in level. In the above-mentioned protective circuit 3, the high voltage applied to the signal input terminal 2, at the time of passing through the resistor R, varies from its sharp waveform to a relatively gentle waveform, and this voltage of gentle waveform is inputted to the pn junction of the MOS transistor 4 and is thus clamped to a specified voltage. Accordingly, the MOS transistor 1 is protected from being broken down.
FIG. 2 shows a plan pattern of the protective circuit 3 shown in FIG. 1. In FIG. 2, an aluminium wire 6 is led out from a bonding pad 5, and is connected at one end to a first end 8 of the resistor R through a contact hole 7. This resistor R is formed of a diffusion layer or polycrystalline silicon layer and, after it is wired over a relatively large length, is connected to a drain diffusion layer 4a of the MOS transistor 4, and is also connected to a gate electrode 11 of the MOS transistor 1 through contact holes 9 and 10. Note here that a drain diffusion layer of the MOS transistor 1 is designated by the reference numeral la, while a source diffusion layer thereof is designated by the reference numeral lb. In addition, a drain diffusion layer of the MOS transistor 4 is designated by the reference numeral 4a, a source diffusion layer thereof by the reference numeral 4b and a gate electrode thereof by the reference numeral 12. The power source Vss has its line 13 connected to the source diffusion layer 4b through a contact hole 14 and connected to the gate electrode 12 through a contact hole 15. The resistor R usually has a resistance value of 500 to several kilo-ohms and a time constant of 1 to 5 nS. That is, this time constant causes a decrease in level of the peak voltage of a pulse having a sharp rise applied to the first end 8 of the resistor R and is so adjusted as to permit a forward or backward response at the diffusion layer of the MOS transistor 4.
Conventionally, the protection of the gate oxide layer of the MOS transistor 1 was effected solely by the use of the above-mentioned protective circuit 3. With the progress of the techniques concerned, however, the gate oxide layer of the MOS transistor 1 has become thinner than in the prior art. This makes it very difficult to design the protective circuit 3 accordingly. Because the use of the protective circuit 3 alone is insufficient to protect the thin gate oxide layer of the MOS transistor 1, the breakdown of the MOS transistor 1 occurs very often.
In an effort to prevent the breakdown of the MOS transistor 1, the inventor of the present application has made various investigations into the causes of this type of breakdown and, as a result, has found that the breakdown occurs at specific portions of the insulation layer. Reference will now be made to the said result of these investigations by the use of FIGS. 3 and 4. As shown in FIG. 3, the regions where the breakdown of the gate insulation layer occurs are the side edge portions 11a and 11b (the portions having small radii of curvature and being represented by dotted lines a and b) of the gate electrode (polycrystalline silicon) 11. The side edge portions are located in the directions of the source and drain regions, and it has been confirmed that breakdown does not occur at a central portion 11c of the gate electrode 11. To explain in more in detail by the use of a sectional view shown in FIG. 4, the portion of the insulation layer 16 which is located beneath the central portion 11c has a uniform distribution of electric lines of force 17 and is therefore kept from breaking down. However, the electric lines of force from the side edge portion 11a are concentrated, as shown in FIG. 4, since the radius of curvature thereof is small. Accordingly, the portion of the insulation layer beneath this side edge portion 11a receives an extremely high electric field and it has thus been proved that this insulation layer portion is broken down owing to discharge attributable to the application of this electric field. For the purpose of decreasing the degree of concentration of the electric lines of force at the side edge portion 11a, it is contemplated to form the polycrystalline silicon gate electrode 11 by patterning based on the use of etching techniques, and thereafter to perform what is called "after oxidation" directed to oxidizing the surface of the electrode 11, thereby enlarging both the radius of curvature of the side edge portion 11a and the thickness of the gate oxide layer including this side edge portion. However, it is not possible to make the radius of curvature of the side edge portion 11a larger than the thickness of the gate electrode. When the "after oxidation" step is excessively performed, the thickness of the gate electrode 11 is decreased and this will decrease the radius of curvature of the side edge portion 11a. This undesirably affects the width of the gate electrode and the depth of the diffusion layer. This means that a limitation is imposed upon the degree of the "after oxidation" which is possible. It is therefore impossible to greatly increase the insulation withstand voltage of the MOS transistor 1.
On the other hand, the protective circuit shown in FIG. 2 is in some cases so constructed as to have a plan pattern as shown in FIG. 9. The protective circuit shown in FIG. 9 is different from that shown in FIG. 2 in that a second terminal of the resistor R and diffusion layer 4a of the MOS transistor 4 is connected by means of an aluminium lead 19 through contact holes 9 and 18. In FIG. 9, the same parts are denoted by the same reference notations as in FIG. 2.
Referring to FIG. 9, as previously mentioned in connection with FIG. 2, the resistor R has a resistance value of, for example, 500 to several kilo-ohms and a time constant of, for example, 1 to 5 nS. Note here that an insulation layer is interposed, though not shown, between this resistor R and the semiconductor substrate.
Consider the case where this resistor R is formed of a diffusion layer. In this case, upon application of a high voltage to the bonding pad 5, this high voltage is applied to the first end 8 of the resistor R through the aluminium lead 6 and contact hole 7. This gives rise to a breakdown at the first end 8 to cause a local current to pass through the same. In a CMOS (Complementary MOS transistor, not shown) a latch-up phenomenon (this indicates the phenomenon wherein a large current flows due to input noises and the like) is liable to occur. Therefore, it is preferable to use polycrystalline silicon as the material of the resistor R. Even in this case, however, the protective circuit for the transistor to be protected is broken down according to a circuit condition. Preventing the dielectric breakdown of the protective circuit of the transistor to be protected (for example, the transistor 1 of FIG. 1) has the same significance as directly preventing the dielectric breakdown of the transistor to be protected. With this in mind, the inventor of this application has made investigations of the dielectric breakdown of the resistor R, the results being explained with reference to FIGS. 9 to 11.
That is, the electric lines of force are concentrated to a remarkable extent in the regions beneath the side edge portions 20a and 20b of the resistor R of FIG. 10, with the result that the insulation layer falling under these regions is broken down. On the other hand, the region located beneath the central portion 20c of the resistor R has a uniform electric-line-of-force distribution, with the result that the insulation layer falling under this region is freed from breakdown. FIG. 11 shows a distribution of electric lines of force in a sectional area taken along the line XI--XI of FIG. 10. It is seen from FIG. 11 that the electric lines of force are remarkably concentrated particularly in the side edge portion 20a.
It has thus been concluded from the said results of investigation that it will be possible to prevent the breakdown of the gate insulation layer of the MOS transistor 1 to be protected by decreasing the degree of concentration of electric lines of force at the side edge portions of the gate electrode 11. It has also been concluded that the breakdown of the insulation layer portion beneath the resistor R of the protective circuit can be prevented by decreasing the degree of concentration of electric lines of force at the side edge portions of the resistor R.